1. Field of the Invention
The present invention generally relates to processing instructions in a computer system. More particularly, a system for processing out of order load and store instructions is provided with the capability to check for the correct execution of load operations relative to store operations.
2. Description of Related Art
Currently, computer systems are generally available that provide for out of order execution of load and store operations. It is known in the art that processing speed is enhanced if store instructions can be executed after the load instructions, i.e. delay executing the store operations as long as possible. However, a problem exists for certain sequences of instructions since data that is to be loaded from a particular memory address may not have had the correct value previously stored therein. In this case, the store instruction must precede the load instruction. The present invention detects this situation and reloads the queue with the required instruction.
U.S. Pat. No. 4,630,195 describes a system for determining data dependency wherein data transfer commands are generated and a register in local storage is assigned to the data being transferred. A tag that identifies the register in which the data is stored and subsequent data transfer is compared to the stored tags to determine any potential dependencies. IBM Technical Disclosure Bulletin Vol. 30, No. 1, June 1987, Pages 191-192, discusses a problem using pipelined architecture wherein during the execution of a store instruction the possibility exists that the data could already be stored in a memory location previously loaded into the pipeline. An expression is derived that will determine if the difference between a program counter and the memory address is equal to one or two, which would be the case if the data is in a memory location already loaded into the pipeline.
U.S. Pat. No. 4,965,716 describes a priority queue wherein elements are kept in a unsorted stack. The stack is searched for the next highest priority element after the highest priority element has been read from a holding register. A priority comparison is implemented to determine the highest priority element. In U.S. Pat. No. 4,574,349 a program instruction calls for transfer of data from a particular main storage location to a general purpose register. This system uses pointers to allow subsequent load instructions involving the same particular main storage location to make data stored in a hardware register immediately available to a central processing unit if the data from the previous load instruction is still stored in one of the hardware registers.
U.S. Pat. No. 4,697,233 ensures data integrity by including a compare stack in a computer system having a pipelined architecture. The stack structure is partially duplexed such that a predetermined number of bits of each data word are stored in a compare stack. At readout, the bits are available for comparison to bits stored in the stack registers to determine that proper decoding has occurred, thereby ensuring data integrity of data in the pipeline.
U.S. Pat. No. 4,638,429 discusses a data processing apparatus using pipeline control that includes an Operand Store Conflict (OSC) circuit for detecting if a succeeding instruction uses an operand to be modified by a preceding instruction whose store operation has not been completed. The OSC detects the execution result of an in order store instruction whose store operation has not been completed is utilized as an operand of a fetch instruction which exceeds the store operation. When a conflict is detected and a store operation is the preceding instruction, a control unit aligns the fetched operand to the operand position of the succeeding instruction and merges them accordingly.
The prior art does not provide any type of system which compares load and store operations to allow for out of order execution of instructions. Some conventional systems are capable of determining any data dependency conflicts that may be present prior to the execution of the instructions, but do not compare the sequence of data load and store operations subsequent to execution of the instructions. In fact, it is not possible to detect load and store conflicts prior to execution, since the memory address for the store data is not generated until the store instruction is executed. Conflicts between data load and store operations occur fairly infrequently, however it is essential that these conditions be detected and corrected. Failure to correct these conflicts will result in processing errors, such as incorrect data, and the like. Thus, it can be seen that a need exists for a system that can detect out of order load and store instructions which cause conflicts when executed.